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LAN91C100 advance information feast? fast ethernet controller features dual speed csma/cd engine (10 mbps and 100 mbps) compliant with ieee 802.3 100base-t specification supports 100base-tx, 100base-t4, and 10base-t physical interfaces 32 bit wide data path (into packet buffer memory) support for 32 and 16 bit buses support for 32, 16 and 8 bit cpu accesses synchronous, asynchronous and burst dma interface mode options 128 kbyte external memory built-in transparent arbitration for slave sequential access architecture flat mmu architecture with symmetric transmit and receive structures and queues mii (media independent interface) compliant mac-phy interface (compliant with emerging mii standard interface) mii management serial interface seven wire interface to 10 mbps endec (lan83c694) eeprom-based setup 208 pin pqfp and tqfp package general description the LAN91C100 feast is a high-speed network controller designed to facilitate the implementation of fast ethernet adapters and connectivity products. it contains a dual speed csma/cd engine that implements the mac portion of the csma/cd protocol at 10 and 100 mbps and couples it with a lean and fast data and control path system architecture to ensure data movement with no bottlenecks at 100 mbps. memory management is handled using a unique mmu (memory management unit) architecture and a 32-bit wide data path. this i/o mapped architecture can sustain back-to-back frame transmission and reception for superior data throughput and optimal performance. it also dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host cpu from performing these housekeeping functions. the total memory size is 128 kbytes (external), equivalent to a total chip storage (transmit and receive) of 64 outstanding packets. feast provides a flexible slave interface for easy connectivity with industry-standard buses. the bus interface unit (biu) can handle synchronous as well as asynchronous buses, with different signals being used for each one. feast's bus interface supports synchronous buses like the vesa local bus, as well as burst mode dma for eisa environments. asynchronous bus support for isa is supported
2 table of contents features ................................ ................................ ................................ ................................ ........ 1 general description ................................ ................................ ................................ .................. 1 pin configuration ................................ ................................ ................................ ....................... 3 description of pin functions ................................ ................................ ................................ . 4 functional description ................................ ................................ ................................ .......... 14 data structures and registers ................................ ................................ .......................... 17 board setup information ................................ ................................ ................................ ....... 59 application considerations ................................ ................................ ................................ .. 62 operational description ................................ ................................ ................................ ........ 69 maximum guaranteed ratings ................................ ................................ ........................ 69 dc electrical characteristics ................................ ................................ ..................... 69 timing diagrams ................................ ................................ ................................ ......................... 72 80 arkay drive hauppauge , ny 11788 (516) 435-6000 fax (516) 273-3123
3 even though isa cannot sustain 100 mbps traffic. fast ethernet could be adopted for isa- based nodes on the basis of the aggregate traffic benefits. feast is software-compatible with the existing lan9000 family of products and can use current lan9000 drivers in 16- and 32-bit intel x86- based environments. two different interfaces are supported on the network side. the first is a conventional seven wire endec interface that connects to the lan83c694 for 10base-t and coax 10 mbps ethernet networks. the second interface follows the mii (media independent interface) specification draft standard, consisting of 4 bit wide data transfers at the nibble rate. feast also interfaces to the mii serial management protocol. four i/o ports (one input and three output pins) are provided for lan83c694 configuration. pin configuration LAN91C100 208 pin pqfp and tqfp nlnk txen xtal1 xtal2 vdd miisel ncsout nc tx25 vdd rx_er rx_dv ios0 gnd ios1 ios2 rx25 col100 crs100 rxd0 rxd1 rxd2 vdd rxd3 txd0 txd1 vdd txd2 txd3 txen100 nrwe0 gnd rd7 rd6 rd5 rd4 nc rd3 rd2 rd1 vdd rd0 rd15 rd14 rd13 gnd rd12 rd11 rd10 gnd eneep eedo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 d8 vdd d9 d10 d11 d12 gnd d13 d14 d15 gnd d16 vdd d17 d18 d19 gnd d20 d21 vdd d22 d23 gnd d24 gnd vdd d25 d26 gnd d27 d28 d29 d30 gnd d31 nrdyrtn nldev vdd nsrdy lclk 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 c r s c o l r x d a v d d r b i a s a g n d l b k t x d g n d r x c m d i t x c m d o n f s t e p a u i s e l a e n m c l k v d d n d a t a c s i n t r 3 i n t r 2 i n t r 1 v d d g n d w / n r n c y c l e r e s e t n v l b u s g n d v d d n w r n r d i n t 0 a r d y g n d d 0 d 1 d 2 d 3 g n d d 4 d 5 d 6 v d d d 7 n b e 3 n b e 2 n b e 1 n b e 0 a 1 5 a 1 4 a 1 3 2 0 8 2 0 7 2 0 6 2 0 5 2 0 4 2 0 3 2 0 2 2 0 1 2 0 0 1 9 9 1 9 8 1 9 7 1 9 6 1 9 5 1 9 4 1 9 3 1 9 2 1 9 1 1 9 0 1 8 9 1 8 8 1 8 7 1 8 6 1 8 5 1 8 4 1 8 3 1 8 2 1 8 1 1 8 0 1 7 9 1 7 8 1 7 7 1 7 6 1 7 5 1 7 4 1 7 3 1 7 2 1 7 1 1 7 0 1 6 9 1 6 8 1 6 7 1 6 6 1 6 5 1 6 4 1 6 3 1 6 2 1 6 1 1 6 0 1 5 9 1 5 8 1 5 7 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 e e d i e e s k e e c s r d 9 n r w e 1 n c r d 8 r d 2 3 r d 2 2 r d 2 1 v d d r d 2 0 r d 1 9 g n d r d 1 8 r d 1 7 r d 1 6 r d 3 1 r d 3 0 n c n r w e 2 v d d g n d r d 2 9 r d 2 8 r d 2 7 r d 2 6 r d 2 5 r d 2 4 g n d v d d r a 2 v d d n r w e 3 r a 3 r a 4 r a 1 2 r a 5 r a 6 r a 1 3 r c v d m a g n d n a d s r a 7 n r o e r a 1 1 r a 8 r a 1 0 r a 9 r a 1 5 r a 1 4 r a 1 6
4 description of pin functionsof pin functionspin functions pqfp/tqfp pin no. name symbol buffer type description 148-159 address a4-a15 i input. decoded by the LAN91C100 to determine accesses to its registers. 145-147 address a1-a3 i input. used by the LAN91C100 for internal register selection. 193 address enable aen i input. used as an address qualifier. address decoding is only enabled when aen is low. 160-163 nbyte enable nbe0-nbe3 i input. used during LAN91C100 register accesses to determine the width of the access and the register(s) being accessed. nbe0-nbe3 are ignored when ndatacs is low (burst accesses) because 32 bit transfers are assumed. 173-170, 168-166, 164,144, 142-139, 137-135, 133, 131-129, 127,126, 124,123, 121,118, 117, 115-112, 110 data bus d0-d31 i/o24 bidirectional. 32 bit data bus used to access the LAN91C100's internal registers. data bus has weak internal pullups. supports direct connection to the system bus without external buffering. for 16 bit systems, only d0-d15 are used. 182 reset reset is input. this input is not considered active unless it is active for at least 100ns to filter narrow glitches. 95 naddress strobe nads is input. address strobe. for systems that require address latching, the rising edge of nads indicates the latching moment for a1- a15 and aen. all LAN91C100 internal functions of a1-a15, aen are latched except for nldev decoding. 183 ncycle ncycle i input. this active low signal is used to control LAN91C100 synchronous bus cycles.
5 description of pin functionsof pin functionspin functions pqfp/tqfp pin no. name symbol buffer type description 184 write/ nrea d w/ nr i input. defines the direction of synchronous cycles. write cycles when high, read cycles when low. 181 nvl bus access nvlbus ip input. when low the LAN91C100 synchronous bus interface is configured for vl bus accesses. otherwise the LAN91C100 is configured for eisa dma burst accesses. does not affect the asynchronous bus interface. 105 local bus clock lclk i input. used to interface synchronous buses. maximum frequency is 50 mhz. limited to 8.33 mhz for eisa dma burst mode. 175 asynchron- ous ready ardy od16 open drain output. ardy may be used when interfacing asynchronous buses to extend accesses. its rising (access completion) edge is controlled by the xtal1 clock and therefore asynchronous to the host cpu or bus clock. 106 nsynchron- ous ready nsrdy o16 output. this output is used when interfacing synchronous buses and nvlbus=0 to extend accesses. this signal remains normally inactive, and its falling edge indicates completion. this signal is synchronous to the bus clock lclk. 109 nready return nrdyrtn i input. this input is used to complete synchronous read cycles. in eisa burst mode it is sampled on falling lclk edges, and synchronous cycles are delayed until it is sampled high. 176 187-189 interrupt int0-int3 o24 outputs. only one of these interrupts is selected to be used; the other three are tri- stated. the selection is determined by the value of int sel1-0 bits in the configuration register.
6 description of pin functionsof pin functionspin functions pqfp/tqfp pin no. name symbol buffer type description 108 nlocal device nldev o16 output. this active low output is asserted when aen is low and a4-a15 decode to the LAN91C100 address programmed into the high byte of the base address register. nldev is a combinatorial decode of unlatched address and aen signals. 177 nread strobe nrd is input. used in asynchronous bus interfaces. 178 nwrite strobe nwr is input. used in asynchronous bus interfaces. 190 ndata path chip select ndatacs ip input. when ndatacs is low, the data path can be accessed regardless of the values of aen, a1-a15 and the content of the bank select register. ndatacs provides an interface for bursting to and from the LAN91C100 32 bits at a time. 54 eeprom clock eesk o4 output. 4 m sec clock used to shift data in and out of the serial eeprom. 55 eeprom select eecs o4 output. used for selection and command framing of the serial eeprom. 52 eeprom data out eedo o4 output. connected to the di input of the serial eeprom. 53 eeprom data in eedi id input. connected to the do output of the serial eeprom. 13,15,16 i/o base ios0-ios2 ip input. external switches can be connected to these lines to select between predefined eeprom configurations. 51 enable eeprom eneep ip input. enables (when high or open) LAN91C100 accesses to the serial eeprom. must be grounded if no eeprom is connected to the LAN91C100.
7 description of pin functionsof pin functionspin functions pqfp/tqfp pin no. name symbol buffer type description 42, 40-38, 36-33, 59,56, 49-47, 45-43, 69-67, 65,64, 62-60, 81-76, 71,70 ram data bus rd0-rd31 i/o4p bidirectional. carries the local buffer memory read and write data. reads are always 32 bits wide. writes are controlled individually at the byte level. 84,87, 88,90, 91,96, 99,101, 100,98, 89,92, 103,102, 104 ram address bus ra2-ra16 o4 outputs. this bus specifies the buffer ram doubleword being accessed by the LAN91C100. 97 nroe o4 output. used to read a doubleword from buffer ram. 31,57, 73,86 nrwe0- rwe3 o4 outputs. used to write any byte, word or dword in ram. 93 nreceive dma nrcvdma o4 output. this pin is active during LAN91C100 write memory cycles of receive packets. 3 4 crystal 1 crystal 2 xtal1 xtal2 i clk an external 25 mhz crystal is connected across these pins. if a ttl clock is supplied instead, it should be connected to xtal1 and xtal2 should be left open. 5,10, 23,27, 41,63, 74,83, 85,107, 119,125, 132,143, 165,179, 186,191 power vdd +5v power supply pins. 205 analog power avdd +5v analog power supply pin.
8 description of pin functionsof pin functionspin functions pqfp/tqfp pin no. name symbol buffer type description 14,32, 46,50, 66,75, 82,94, 111,116, 120,122, 128,134, 138,169, 174,180, 185,200 ground gnd ground pins. 203 analog ground agnd analog ground pin. 2 transmit enable txen o4 output. used for 10 mbps endec. this pin stays low when miisel is high. 201 transmit data txd o4 nrz transmit data output for 10 mbps endec interface. 208 carrier sense crs id input. carrier sense from 10 mbps endec interface. this pin is ignored when miisel is high. 207 collision detection col id input. collision detection indication from 10 mbps endec interface. this pin is ignored when miisel is high. 206 receive data rxd ip nrz receive data input from 10 mbps endec interface. this pin is ignored when miisel is high. 197 transmit clock txc ip input. 10 mhz transmit clock used in 10 mbps operation. this pin is ignored when miisel is high. 199 receive clock rxc ip input. 10mhz receive clock recovered by the 10 mbps endec. this pin is ignored when miisel is high. 202 loopback lbk o4 output. active when loop bit is set (tcr bit 1). independent of port selection (miisel=x).
9 description of pin functionsof pin functionspin functions pqfp/tqfp pin no. name symbol buffer type description 1 nlink status nlnk ip input. general purpose input port used to convey link status (ephsr bit 14). independent of port selection (miisel=x). 195 nfullstep nfstep o4 output. non volatile output pin. driven by inverse of fullstep (config bit 10). independent of port selection (mii sel=x). 6 mii select miisel o4 output. non volatile output pin. driven by mii select (config bit 15). high indicates the mii port is selected, low indicates the 10 mbps endec is selected. 194 aui select auisel o4 output. non volatile output pin. driven by aui select (config bit 8). independent of port selection (miisel=x). 30 transmit enable 100 mbps txen100 o4 output to mii phy. envelope to 100 mbps transmission. this pin stays low if miisel is low. 19 carrier 100 mbps crs100 ip input from mii phy. envelope of packet reception used for deferral and backoff purposes. this pin is ignored when miisel is low. 12 receive data valid rx_dv id input from mii phy. envelope of data valid reception. used for receive data framing. this pin is ignored when miisel is low. 18 collision detect 100 mbps col100 id input from mii phy. collision detection input. this pin is ignored when miisel is low. 25,26, 28,29 transmit data txd0-txd3 o4 outputs. transmit data nibble to mii phy. 9 transmit clock tx25 ip input. transmit clock input from mii. nibble rate clock (25 mhz). this pin is ignored when miisel is low. 17 receive clock rx25 ip input. receive clock input from mii phy. nibble rate clock. this pin is ignored when miisel is low. 20,21, 22,24 receive data rxd0- rxd3 i inputs. received data nibble from mii phy. these pins are ignored when miisel is low.
10 description of pin functionsof pin functionspin functions pqfp/tqfp pin no. name symbol buffer type description 198 manage- ment data input mdi ip mii management data input. 196 manage- ment data output mdo o4 mii management data output. 192 manage- ment clock mclk o4 mii management clock. 11 receive error rx_er id input. indicates a code error detected by phy. used by the LAN91C100 to discard the packet being received. the error indication reported for this event is the same as a bad crc (receive status word bit 13). this pin is ignored when miisel is low. 204 bias resistor rbias analog input a bias resistor is connected between this pin and ground. nominal value is tbd. 7 nchip select output ncsout o4 output. chip select provided for mapping of phy functions into LAN91C100 decoded space. active on accesses to LAN91C100's eight lower addresses when the bank selected is 7.
11 tabl e 1 - LAN91C100 pin requirements function pin symbols number of pins system address bus a1-a15, aen, nbe0-nbe3 20 system data bus d0-d31 32 system control bus reset, nads, lclk, ardy, nrdyrtn, nsrdy, int0-int3, nldev, nrd, nwr, ndatacs, ncycle, w/ nr, nvlbus 17 serial eeprom eedi, eedo, eecs, eesk, eneep, ios0-ios2 8 ram data bus rd0-rd31 32 ram address bus ra2-ra16 15 ram control bus nroe, nrwe0-nrwe3, rcvdma 6 crystal oscillator xtal1, xtal2 2 power vdd, avdd 19 ground gnd, agnd 21 external endec 10 mbps txen, txd, crs, col, rxd, txc, rxc, lbk, nlnk, nfstep, auisel, miisel 12 physical interface 100 mbps txen100, crs100, col100, rx_dv, rx_er, txd0-txd3, rxd0-rxd3, mdi, mdo, mclk 16 clocks tx25, rx25 2 miscellaneous rbias, ncsout 2 total 204
12
13 bus interface unit arbiter memory management unit direct memory access media access control serial eeprom rd fifo wr fifo address data control ram 25 mhz 10 mb interface 100 mb media independent interface figure 1 - LAN91C100 feast block diagram
14 figure 2 - LAN91C100 feast system diagram address control data address control data system bus serial eeprom 1o mbps mii rd0-31 oe,we ra sram 32kx8 1 2 3 4 LAN91C100 feast lan83c694 10base-t interface 10base-t 100base-t4 interface chip 100base-t4 100base-tx interface logic 100base-tx or
15 functional description description of blocks clock generator block the LAN91C100's clock generator uses a 25 mhz crystal connected to pins xtal1 xtal2 and generates two free running clocks: 1) 50 mhz free running clock - supplied to the dma and the arbiter blocks. 2) 25 mhz free running clock - used to run the eph during reset or when no tx25 is present. other clocks: 3) txclk and rxclk are 10 mhz clock inputs. these clocks are generated by the external endec in 10 mbps mode and are only used by the csma/cd block. 4) tx25 is an input clock. it will be the nibble rate of the particular phy connected to the mii (2.5 mhz for a 10 mbps phy, and 25 mhz for a 100 mbps phy). 5) rx25 - this is the mii nibble rate receive clock used for sampling received data nibbles and running the receive state machine (2.5 mhz for a 10 mbps phy, and 25 mhz for a 100 mbps phy). 6) lclk - bus clock - used by the biu for synchronous accesses. maximum frequency is 50 mhz for vl bus mode, and 8.5 mhz for eisa slave dma. csma/cd block this is a 16-bit oriented block, with fully- independent transmit and receive logic. the data path in and out of the block consists of two 6-bit wide uni- directional fifos interfacing the dma block. the dma port of the fifo stores 32 bits exploiting the 32-bit data path into memory. the control path consists of a set of registers interfaced to the cpu via the biu. dma block this block accesses packet memory on the csma/cd's behalf, fetching transmit data and storing received data. it interfaces the csma/cd transmit and receive fifos on one side, and the arbiter block on the other. the data path is 32 bits wide. the dma machine is able to support full duplex operation. independent receive and transmit counters are used. transmit and receive cycles are alternated when simultaneous receive and transmit accesses are needed. arbiter block the arbiter block sequences accesses to packet ram requested by the biu and by the dma blocks. biu requests represent pipelined cpu accesses to the data register, while dma requests represent csma/cd data movement. the external memory devices used are 25ns 32kx8 sram. the cycle time for cpu consecutive accesses to the data path is 80ns/doubleword. this time includes arbitration and csma memory cycles. the arbiter is also responsible for controlling the nrwe0-nrwe3 lines as a function of the bytes being written. read accesses are always 32 bits wide, and the arbiter steers the appropriate byte(s) to the appropriate lanes as a function of the address. the cpu data path consists of two uni - directional fifos mapped at the data register location. these fifos can be accessed in any
16 combination of bytes, word, or doublewords. the arbiter will indicate 'not ready' whenever a cycle is initiated that cannot be satisfied by the present state of the fifo. the depth of the fifos will accommodate the worst case arbitration and byte access alignment pattern while still preserving the cpu cycle time when accessing the data register. mmu block the hardware memory management unit is similar to the lan91c90's mmu. it does dynamic memory allocation and queuing of transmit and receive packets, and it determines the value of the transmit and receive interrupts as a function of the queues. the page size is still 2k, and with a maximum memory size of 128k the mmu uses 64x6 fifos. mir and mcr values are interpreted in 512 byte units. biu block the bus interface unit can handle synchronous as well as asynchronous buses; different signals are used for each one. transparent latches are added on the address path using rising nads for latching. when working with an asynchronous bus like isa, the read and write operations are controlled by the edges of nrd and nwr. ardy is used for notifying the system that it should extend the access cycle. the leading edge of ardy is generated by the leading edge of nrd or nwr while the trailing edge of ardy is controlled by the LAN91C100's internal clock and, therefore, is asynchronous to the bus. in the synchronous vl bus type mode, ncycle and lclk are used for read and write operations. completion of the cycle may be determined by using nsrdy. nsrdy is controlled by lclk and is synchronous to the bus. direct 32-bit access to the data path is supported by using the ndatacs input . by asserting ndatacs , external dma-type of devices will bypass the biu address decoders and can sequentially access memory with no cpu intervention. ndatacs accesses can be used in the dma burst mode (nvlbus=1) or in asynchronous cycles. these cycles must be 32-bit cycles. please refer to the correspond ing timing diagrams for details on these cycles. mac-phy interface two separate interfaces are defined; one for the 10 mbps bit rate interface and one for the mii 100 mbps and 10 mbps nibble rate interface. the 10 mbps endec interface comprises the signals used for interfacing ethernet endecs. the 100 mbps interface follows the mii draft standard for 100 mbps 802.3 networks, and it is based on transferring nibbles between the mac and the phy. for the mii interface, transmit data is clocked out using the tx25 clock input, while receive data is clocked in using rx25. switching between the endec and mii interfaces is controlled by the mii select bit in the configuration register. the miisel pin reflects the value of the bit and may be used to control external multiplexing logic. mii management interface block phy management through the mii management interface is supported by the LAN91C100 by providing the means to drive a tri-statable data output, a clock, and reading an input. timing and framing for each management command is be generated by the cpu.
17 serial eeprom interface block this block is responsible for reading the serial eeprom upon hardware reset (or equivalent command) and defining defaults for some key registers. a write operation is also implemented by this block which, under cpu command, will program specific locations in the eeprom. this block is an autonomous state machine, and it controls the LAN91C100's internal data bus during active operation. bus interface arbiter mmu buffer ram csma/cd data bus address bus control eeprom eeprom write data reg read data reg tx fifo tx compl fifo rx fifo dma interface address data transmit receive figure 3 - LAN91C100 internal block diagram with data path
18 data structures and registers packet format in buffer memory the packet format in memory is similar for the transmit and receive areas. the first word is reserved for the status word, the next word is used to specify the total number of bytes, and it is followed by the data area. the data area holds the packet itself. figure 4 ? data packet format transmit packet receive packet status word written by csma upon transmit completion (see status register) written by csma upon receive completion (see rx frame status word) byte count written by cpu written by csma data area written/modified by cpu written by csma control byte written by cpu to control odd/even data bytes written by csma; also has odd/even bit reserved byte count status word last data byte (if odd) bit 0 bit 15 ram offset (decimal) 0 2 4 2046 max control byte data area
19 byte count - divided by two, it defines the total number of words, including the status word, the byte count word, the data area and the control byte. the receive byte count always appears as even, the oddfrm bit of the receive status word indicates if the low byte of the last word is relevant. the transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory. data area - the data area starts at offset 4 of the packet structure, and it can extend for up to 2043 bytes. the data area contains six bytes of destination address followed by six bytes of source address, followed by a variable length number of bytes. on transmit, all bytes are provided by the cpu, including the source address. the LAN91C100 does not insert its own source address. on receive, all bytes are provided by the csma side. the 802.3 frame length word (frame type in ethernet) is not interpreted by the LAN91C100. it is treated transparently as data both for transmit and receive operations. control byte - for transmit packets the control byte is written by the cpu as: x x odd crc 0 0 0 0 odd if set, indicates an odd number of bytes, with the last byte being right before the control byte. if clear, the number of data bytes is even and the byte before the control byte is not transmitted. crc when set, crc will be appended to the frame. this bit has only meaning if the nocrc bit in the tcr is set. for receive packets the control byte is written by the controller as: 0 1 odd 0 0 0 0 0 odd if set, indicates an odd number of bytes, with the last byte being right before the control byte. if clear, the number of data bytes is even and the byte before the control byte should be ignored.
20 receive frame status word this word is written at the beginning of each receive frame in memory. it is not available as a register. high byte algn err brod cast bad crc odd frm toolng too short low byte hash value mult cast 5 4 3 2 1 0 algnerr frame had alignment error. when mii sel=1 alignment error is set when badcrc=1 and an odd number of nibbles were received between sfd and rx_dv going inactive. when mii sel=0 alignment error is set when badcrc=1 and the number of bits received between sfd and the crs going inactive is not an octet multiple. brodcast receive frame was broadcast. badcrc frame had crc error, or rx_er was asserted during reception. oddfrm this bit, when set, indicates that the received frame had an odd number of bytes. toolng frame length was longer than 802.3 maximum size (1518 bytes on the cable). tooshort frame length was shorter than 802.3 minimum size (64 bytes on the cable). hash value provides the hash value used to index the multicast registers. can be used by receive routines to speed up the group address search. the hash value consists of the six most significant bits of the crc calculated on the destination address, and maps into the 64 bit multicast table. bits 5,4,3 of the hash value select a byte of the multicast table, while bits 2,1,0 determine the bit within the byte selected. examples of the address mapping: address hash value 5-0 multicast table bit ed 00 00 00 00 00 0d 00 00 00 00 00 01 00 00 00 00 00 2f 00 00 00 00 00 000 000 010 000 100 111 111 111 mt-0 bit 0 mt-2 bit 0 mt-4 bit 7 mt-7 bit 7 multcast receive frame was multicast. if hash value corresponds to a multicast table bit that is set, and the address was a multicast, the packet will pass address filtering regardless of other filtering criteria.
21 i/o space the base i/o space is determined by the ios0-2 inputs and the eeprom contents. to limit the i/o space requirements to 16 locations, the registers are assigned to different banks. the last word of the i/o area is shared by all banks and can be used to change the bank in use. registers are described using the following convention: offset name type symbol high byte bit 15 bit14 bit 13 bit 12 bit 11 bit 10 bit9 bit8 x x x x x x x x low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x x x x offset defines the address offset within the iobase where the register can be accessed at, provided the bank select has the appropriate value. the offset specifies the address of the even byte (bits 0-7) or the address of the complete word. the odd byte can be accessed using address (offset + 1). some registers (like the interrupt ack., or like interrupt mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. regardless of the functional description, all registers can be accessed as doublewords, words or bytes. the default bit values upon hard reset are highlighted below each register. table 2 - internal i/o space mapping bank0 bank1 bank2 bank3 0 tcr config mmu command mt0-1 2 eph status base pnr/arr mt2-3 4 rcr ia0-1 fifo ports mt4-5 6 counter ia2-3 pointer mt6-7 8 mir ia4-5 data mgmt a mcr general purpose data revision c reserved (0) control interrupt ercv e bank select bank select bank select bank select a special bank (bank7) exists to support the addition of external registers.
22 bank select register offset e name bank select register type read/write symbol bsr high byte 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 low byte bs2 bs1 bs0 x x x x x 0 0 0 bs2, bs1, bs0 determine the bank presently in use. this register is always accessible and is used to select the register bank in use. the upper byte always reads as 33h and can be used to help determine the i/o location of feast. the bank select register is always accessible regardless of the value of bs0-2. note that the bank select register can be accessed as a doubleword at offset ch , as a word at offset eh , or as at offset fh , however a doubleword write to offset ch will write the bank select register but will not write the registers ch and dh . bank 7 has no internal registers other than the bank select register itself. on valid cycles where bank7 is selected (bs0=bs1=bs2=1), and a3=0, ncsout is activated to facilitate implementation of external registers. note: bank7 does not exist in lan91c9x devices. for backward s/w compatibility bank7 accesses should be done if the revision control register indicates the device is LAN91C100.
23 i/o space - bank0 offset 0 name transmit control register type read/write symbol tcr this register holds bits programmed by the cpu to control some of the protocol transmit options. high byte eph loop stp sqet fduplx mon_ csn nocrc x x 0 0 0 0 x 0 low byte pad_en forcol loop txena 0 x x x x 0 0 0 eph_ loop internal loopback at the eph block. serial data is looped back when set. defaults low. when eph_loop is high, the following transmit outputs are forced inactive: txd0-3=0h, txen100=txen=0, txd=1. the following external inputs are blocked: crs=crs100=0, col=col100=0, rx_dv=rx_er=0. stp_ sqet stop transmission on sqet error. if set, stops and disables transmitter on sqe test error. does not stop on sqet error and transmits next frame if clear. defaults low. fduplx when set it enables full duplex operation. this will cause frames to be received if they pass the address filter regardless of the source for the frame. when clear the node will not receive a frame sourced by itself. mon_ csn when set, the LAN91C100 monitors carrier while transmitting. it must see its own carrier by the end of the preamble. if it is not seen, or if carrier is lost during transmission , the transmitter aborts the frame without crc and turns itself off. when this bit is clear the transmitter ignores its own carrier. defaults low. nocrc does not append crc to transmitted frames when set; allows software to insert the desired crc. defaults to 0 (crc inserted). pad_ en when set, the LAN91C100 will pad transmit frames shorter than 64 bytes with 00. does not pad frames when reset. forcol when set, the transmitter will force a collision by not deferring deliberately. after the collision this bit is reset automatically. this bit defaults low to normal operation. loop loopback . general purpose output port used to control the lbk pin. typically used to put the phy chip in loopback mode. txena transmit enabled when set. transmit is disabled if clear. when the bit is cleared, the LAN91C100 will complete the current transmission before stopping. when stopping due to an error, this bit is automatically cleared.
24 i/o space - bank 0 offset 2 name eph status register type read only symbol ephsr this register stores the status of the last frame transmitted. this register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions. the register can be used for real time values (like txena and link ok). if txena is cleared the register holds the last packet completion status. high byte tx unrn link_ok rx_ovrn ctr_rol exc_def lost carr latcol 0 - nlnk pin 0 0 0 0 0 x low byte tx defr ltx brd sqet 16col ltx mult mul col sngl col tx_suc 0 0 0 0 0 0 0 0 txunrn transmit under run. set if under run occurs, it also clears txena bit in tcr. cleared by setting txena high. this bit should never be set under normal operation. link_ ok general purpose input port driven by nlnk pin inverted. typically used for link test. a transition on the value of this bit generates an interrupt. rx_ ovrn upon fifo overrun, the receiver asserts this bit and clears the fifo. the receiver stays enabled. after a valid preamble has been detected on a subsequent frame, rx_ovrn is de-asserted. the rx_ovrn int bit in the interrupt status register will also be set and stay set until cleared by the cpu. note that receive overruns could occur only if receive memory allocations fail. ctr_ rol counter roll over. when set, one or more 4-bit counters have reached maximum count (15). cleared by reading the ecr register. exc_ def excessive deferral. when set last/current transmit was deferred for more than 1518 * 2 byte times. cleared at the end of every packet sent. lost_ carr lost carrier sense. when set, indicates that carrier sense was not present at end of preamble. valid only if mon_csn is enabled. this condition causes txena bit in tcr to be reset. cleared by setting txena bit in tcr. latcol late collision detected on last transmit frame. if set, a late collision was detected (later than 64 byte times into the frame). when detected, the transmitter jams and turns itself off, clearing the txena bit in tcr. cleared by setting txena in tcr. tx_ defr transmit deferred. when set, carrier was detected during the first 6.4 m sec of the inter frame gap. cleared at the end of every packet sent. ltx_brd last transmit frame was a broadcast.
25 set if frame was broadcast. cleared at the start of every transmit frame. sqet signal quality error test. for 10 mbps systems, the transmitter opens a 1.6 m s window 0.8 m s after transmission is completed and the receiver returns inactive. during this window, the transmitter expects to see the sqet signal from the transceiver. the absence of this signal is a 'signal quality error' and is reported in this status bit. transmission stops and eph int is set if stp_sqet is in the tcr is also set when sqet is set. this bit is cleared by setting txena high. the behavior of this bit for 100 mbps is presently undefined. 16col 16 collisions reached. set when 16 collisions are detected for a transmit frame. txena bit in tcr is reset. cleared when txena is set high. ltx_ mult last transmit frame was a multicast. set if frame was a multicast. cleared at the start of every transmit frame. mulcol multiple collision detected for the last transmit frame. set when more than one collision was experienced. cleared when tx_suc is high at the end of the packet being sent. snglcol single collision detected for the last transmit frame. set when a collision is detected. cleared when tx_suc is high at the end of the packet being sent. tx_ suc last transmit was successful. set if transmit completes without a fatal error. this bit is cleared by the start of a new frame transmission or when txena is set high. fatal errors are: 16 collisions sqet fail and stp_sqet = 1 fifo underrun carrier lost and mon_csn = 1 late collision
26 i/o space - bank 0 offset 4 name receive control register type read/write symbol rcr high byte soft rst filt car 0 0 0 0 strip crc rxen 0 0 0 0 0 0 0 0 low byte almul prms rx_ abort 0 0 0 0 0 0 0 0 soft_ rst software-activated reset. active high. initiated by writing this bit high and terminated by writing the bit low. the LAN91C100's configuration is not preserved except for configuration, base, and ia0-5 registers. eeprom is not reloaded after software reset. filt_ car filter carrier. when set, filters leading edge of carrier sense for 12 bit times (3 nibble times). otherwise recognizes a receive frame as soon as carrier sense is active. (does not filter rx_dv on mii!) strip_ crc when set, it strips the crc on received frames. when clear, the crc is stored in memory following the packet. defaults low. rxen enables the receiver when set. if cleared, completes receiving current frame and then goes idle. defaults low on reset. almul when set, accepts all multicast frames (frames in which the first bit of da is '1'). when clear accepts only the multicast frames that match the multicast table setting. defaults low. prms promiscuous mode. when set, receives all frames. does not receive its own transmission unless it is in full duplex !. rx_ abort this bit is set if a receive frame was aborted due to length longer than 2044 bytes. the frame will not be received. the bit is cleared by reset or by the cpu writing it low.
27 i/o space - bank 0 offset 6 name counter register type read only symbol ecr counts four parameters for mac statistics. when any counter reaches 15 an interrupt is issued. all counters are cleared when reading the register, and do not wrap around beyond 15. high byte number of exc. deferred tx number of deferred tx 0 0 0 0 0 0 0 0 low byte multiple collision count single collision count 0 0 0 0 0 0 0 0 each 4-bit counter is incremented every time the corresponding event, as defined in the eph status register bit description, occurs. note that the counters can only increment once per enqueued transmit packet, never faster; limiting the rate of interrupts that can be generated by the counters. for example, if a packet is successfully transmitted after one collision, the single collision count field is incremented by one. if a packet experiences between two to 16 collisions, the multiple collision count field is incremented by one. if a packet experiences deferral, the number of deferred tx field is incremented by one, even if the packet experienced multiple deferrals during its collision retries. the counter register facilitates maintaining statistics in the auto release mode where no transmit interrupts are generated on successful transmissions. reading the register in the transmit service routine will be enough to maintain statistics.
28 i/o space - bank 0 offset 8 name memory information register type read only symbol mir high byte free memory available (in bytes * 256 * m) 1 1 1 1 1 1 1 1 low byte memory size (in bytes * 256 * m) 1 1 1 1 1 1 1 1 free memory available this register can be read at any time to determine the amount of free memory. the register defaults to the memory size upon reset or upon the reset mmu command. memory size - this register can be read to determine the total memory size. all memory-related information is represented in 256 * m byte units, where the multiplier m is determined by the mcr upper byte. these registers default to ffh, which should be interpreted as 256.
29 i/o space - bank 0 offset a name memory configuration register type lower byte - read/write upper byte - read only symbol mcr high byte memory size multiplier (m) 0 0 1 1 0 1 0 1 low byte memory reserved for transmit (in bytes * 256 * m) 0 0 0 0 0 0 0 0 memory reserved for transmit programming this value allows the host cpu to reserve memory to be used later for transmit, limiting the amount of memory that receive packets can use up. when programmed for zero, the memory allocation between transmit and receive is completely dynamic. when programmed for a non-zero value, the allocation is dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free memory is less or equal to the programmed value. this register defaults to zero upon reset. it is not affected by the reset mmu command. the value written to the mcr is a reserved memory space in addition to any memory currently in use. if the memory allocated for transmit plus the reserved space for transmit is required to be constant (rather than grow with transmit allocations), the cpu should update the value of this register after allocating or releasing memory. the contents of mir as well as the low byte of mcr are specified in 256 * m bytes. the multiplier m is determined by bits 11, 10, and 9 as follows (bits 11, 10 and 9 are read only bits used by the software driver to transparently run on different controllers of the lan9000 family): device bit 11 bit 10 bit 9 m max memory size LAN91C100 0 1 0 2 256*256*2=128k lan91c90 0 0 1 1 256*256*1=64k future 0 1 1 4 256k future 1 0 0 8 512k future 1 0 1 16 1m
30 i/o space - bank1 offset 0 name configuration register type read/write symbol cr the configuration register holds bits that define the adapter configuration and are not expected to change during run-time. this register is part of the eeprom-saved setup. high byte mii select no wait full step aui select 1 x x 0 x 0 0 0 low byte 1 0 reserved int sel1 int sel0 1 0 1 1 0 0 0 x mii select used to select the network interface port. when set, the LAN91C100 will use its mii port and interface a phy device at the nibble rate. when clear, the LAN91C100 will use its 10 mbps endec interface. this bit drives the mii sel pin. switching between ports should be done with transmitter and receiver disabled and no transmit/receive packets in progress. no wait when set, does not request additional wait states. an exception to this are accesses to the data register if not ready for a transfer. when clear, negates iochrdy for two to three clocks on any cycle to the LAN91C100. full step this bit is a general purpose output port. its inverse value drives pin nfstep and it is typically connected to sel pin of the lan83c694c. it can be used to select the signaling mode for the aui, or as a general purpose non-volatile configuration pin. defaults low. aui select this bit is a general purpose output port. its value drives pin auisel and it is typically connected to mode1 pin of the lan83c694c. it can be used to select aui vs. 10base-t, or as a general purpose non-volatile configuration pin. defaults low. int sel1- 0 used to select one out of four interrupt pins. the three unused interrupts are tristated. int sel1 int sel0 pin used 0 0 1 1 0 1 0 1 intr0 intr1 intr2 intr3
31 i/o space - bank1 offset 2 name base address register type read/write symbol bar this register holds the i/o address decode option chosen for the LAN91C100. it is part of the eeprom saved setup, and is not usually modified during run-time. high byte a15 a14 a13 a9 a8 a7 a6 a5 0 0 0 1 1 0 0 0 low byte reserved 0 0 0 0 0 0 0 x a15-a13 and a9- a5 these bits are compared against the i/o address on the bus to determine the iobase for the LAN91C100's registers. the 64k i/o space is fully decoded by the LAN91C100 down to a 16 location space, therefore, the unspecified address lines a4, a10, a11 and a12 must be all zeros. all bits in this register are loaded from the serial eeprom. the i/o base decode defaults to 300h (namely, the high byte defaults to 18h).
32 i/o space - bank1 offset 4 through 9 name individual address registers type read/write symbol iar these registers are loaded starting at word location 20h of the eeprom upon hardware reset or eeprom reload. the registers can be modified by the software driver, but a store operation will not modify the eeprom individual address contents. bit 0 of individual address 0 register corresponds to the first bit of the address on the cable. high byte address 0 0 0 0 0 0 0 0 0 low byte address 1 0 0 0 0 0 0 0 0 high byte address 2 0 0 0 0 0 0 0 0 low byte address 3 0 0 0 0 0 0 0 0 high byte address 4 0 0 0 0 0 0 0 0 low byte address 5 0 0 0 0 0 0 0 0
33 i/o space - bank1 offset a name general purpose register type read/write symbol gpr high byte high data byte 0 0 0 0 0 0 0 0 low byte low data byte 0 0 0 0 0 0 0 0 this register can be used as a way of storing and retrieving non-volatile information in the eeprom to be used by the software driver. the storage is word oriented, and the eeprom word address to be read or written is specified using the six lowest bits of the pointer register. this register can also be used to sequentially program the individual address area of the eeprom, that is normally protected from accidental store operations. this register will be used for eeprom read and write only when the eeprom select bit in the control register is set. this allows generic eeprom read and write routines that do not affect the basic setup of the LAN91C100.
34 i/o space - bank1 offset c name control register type read/write symbol ctr high byte 0 rcv_bad 0 auto release 0 0 0 0 x 0 x x 0 low byte le enable cr enable te enable eeprom select reload store 0 0 0 x x 0 0 0 rcv_ bad when set, bad crc packets are received. when clear bad crc packets do not generate interrupts and their memory is released. auto release when set, transmit pages are released by transmit completion if the transmission was successful (when tx_suc is set). in that case there is no status word associated with its packet number, and successful packet numbers are not even written into the tx completion fifo. a sequence of transmit packets will only generate an interrupt when the sequence is completely transmitted (tx empty int will be set), or when a packet in the sequence experiences a fatal error (tx int will be set). upon a fatal error txena is cleared and the transmission sequence stops. the packet number that failed is the present in the fifo ports register, and its pages are not released, allowing the cpu to restart the sequence after corrective action is taken. le enable link error enable. when set it enables the link_ok bit transition as one of the interrupts merged into the eph int bit. defaults low (disabled). writing this bit also serves as the acknowledge by clearing previous link interrupt conditions. cr enable counter roll over enable. when set it enables the ctr_rol bit as one of the interrupts merged into the eph int bit. defaults low (disabled). te enable transmit error enable. when set it enables transmit error as one of the interrupts merged into the eph int bit. defaults low (disabled). transmit error is any condition that clears txena with tx_suc staying low as described in the ephsr register. eeprom select this bit allows the cpu to specify which registers the eeprom reload or store refers to. when high, the general purpose register is the only register read or written. when low, reload reads configuration, base and individual address, and store writes the configuration and base registers. reload when set, it will read the eeprom and update relevant registers with its contents. clears upon completing the operation. store when set, stores the contents of all relevant registers in the serial eeprom. clears upon completing the operation.
35 note: when an eeprom access is in progress the store and reload bits will be read back as high. the remaining 14 bits of this register will be invalid. during this time attempted read/write operations, other than polling the eeprom status, will not have any effect on the internal registers. the cpu can resume accesses to the LAN91C100 after both bits are low. a worst case reload operation initiated by reset or by software takes less than 750 m sec.
36 i/o space - bank2 offset 0 name mmu command register type write only busy bit readable symbol mmucr this register is used by the cpu to control the memory allocation, de-allocation, tx fifo and rx fifo control. the three command bits determine the command issued as described below: high byte low byte command 0 0 n2 n1 n0/busy x y z 0 command set xyz 000 0) noop - no operation 001 1) allocate memory for tx - n2 ,n1,n0 defines the amount of memory requested as (value + 1) * 256 bytes. namely n2 ,n1,n0 = 1 will request 2 * 256 = 512 bytes. a shift-based divide by 256 of the packet length yields the appropriate value to be used as n2 ,n1,n0. immediately generates a completion code at the allocation result register. can optionally generate an interrupt on successful completion. n2 ,n1,n0 are ignored by the LAN91C100 but should be implemented in the LAN91C100's software drivers for lan9000 compatibility. 010 2) reset mmu to initial state - frees all memory allocations, clears relevant interrupts, resets packet fifo pointers. 011 3) remove frame from top of rx fifo - to be issued after cpu has completed processing of present receive frame. this command removes the receive packet number from the rx fifo and brings the next receive frame (if any) to the rx area (output of rx fifo). 100 4) remove and release top of rx fifo - like 3) but also releases all memory used by the packet presently at the rx fifo output.
37 101 5) release specific packet - frees all pages allocated to the packet specified in the packet number register. should not be used for frames pending transmission. typically used to remove transmitted frames, after reading their completion status. can be used following 3) to release receive packet memory in a more flexible way than 4). 110 6) enqueue packet number into tx fifo - this is the normal method of transmitting a packet just loaded into ram. the packet number to be enqueued is taken from the packet number register. 111 7) reset tx fifos - this command will reset both tx fifos-- thetx fifo holding the packet numbers awaiting transmission and the tx completion fifo. this command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. the reset tx fifos command should only be used when the transmitter is disabled. unlike the reset mmu command, the reset tx fifos does not release any memory. note 1: bits n2 ,n1,n0 bits are ignored by the LAN91C100 but should be used for command 0) to preserve software compatibility with the lan91c92 and future devices. they should be zero for all other commands. note 2: when using the reset tx fifos command, the cpu is responsible for releasing the memory associated with outstanding packets, or re- enqueuing them. packet numbers in the completion fifo can be read via the fifo ports register before issuing the command. note 3: mmu commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it. command sequencing a second allocate command (command 1) should not be issued until the present one has completed. completion is determined by reading the failed bit of the allocation result register or through the allocation interrupt. a second release command (commands 4, 5) should not be issued if the previous one is still being processed. the busy bit indicates that a release command is in progress. after issuing command 5, the contents of the pnr should not be changed until busy goes low. after issuing command 4, command 3 should not be issued until busy goes low. busy bit readable at bit 0 of the mmu command register address. when set indicates that mmu is still processing a release command. when clear, mmu has already completed last release command. busy and failed bits are set upon the trailing edge of command.
38 i/o space - bank2 offset 2 name packet number register type read/write symbol pnr packet number at tx area 0 0 0 0 0 0 0 0 packet number at tx area - the value written into this register determines which packet number is accessible through the tx area. some mmu commands use the number stored in this register as the packet number parameter. this register is cleared by a reset or a reset mmu command. offset 3 name allocation result register type read only symbol arr this register is updated upon an allocate memory mmu command. failed allocated packet number 1 0 0 0 0 0 0 0 failed a zero indicates a successful allocation completion. if the allocation fails the bit is set and only cleared when the pending allocation is satisfied. defaults high upon reset and reset mmu command. for polling purposes, the alloc_int in the interrupt status register should be used because it is synchronized to the read operation. sequence: 1) allocate command 2) poll alloc_int bit until set 3) read allocation result register allocated packet number packet number associated with the last memory allocation request. the value is only valid if the failed bit is clear. note: for software compatibility with future versions, the value read from the arr after an allocation request is intended to be written into the pnr as is, without masking higher bits (provided failed = 0).
39 i/o space - bank2 offset 4 name fifo ports register type read only symbol fifo this register provides access to the read ports of the receive fifo and the transmit completion fifo. the packet numbers to be processed by the interrupt service routines are read from this register. high byte rempty rx fifo packet number 1 0 0 0 0 0 0 0 low byte tempty tx done packet number 1 0 0 0 0 0 0 0 rempty no receive packets queued in the rx fifo. for polling purposes, uses the rcv_int bit in the interrupt status register. top of rx fifo packet number packet number presently at the output of the rx fifo. only valid if rempty is clear. the packet is removed from the rx fifo using mmu commands 3) or 4). tempty no transmit packets in completion queue. for polling purposes, uses the tx_int bit in the interrupt status register. tx done packet number packet number presently at the output of the tx completion fifo. only valid if tempty is clear. the packet is removed when a tx int acknowledge is issued. note: for software compatibility with future versions, the value read from each fifo register is intended to be written into the pnr as is, without masking higher bits (provided tempty and rempty = 0 respectively).
40 i/o space - bank2 offset 6 name pointer register type read/write not empty is a read only bit symbol ptr high byte rcv auto incr. read eten not empty pointer high 0 0 0 0 0 0 0 0 low byte pointer low 0 0 0 0 0 0 0 0 pointer register the value of this register determines the address to be accessed within the transmit or receive areas. it will auto- increment on accesses to the data register when auto incr. is set. the increment is by one for every byte access, by two for every word access, and by four for every double word access. when rcv is set, the address refers to the receive area and uses the output of rx fifo as the packet number, when rcv is clear the address refers to the transmit area and uses the packet number at the packet number register. read determines the type of access to follow. if the read bit is high, the operation intended is a read. if the read bit is low, the operation is a write. loading a new pointer value, with the read bit high, generates a pre-fetch into the data register for read purposes. readback of the pointer will indicate the value of the address last accessed by the cpu (rather than the last pre-fetched). this allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being interrupted. the pointer register should not be loaded until the cpu has verified that the not empty bit is clear to ensure that the data register fifo is empty. on reads, if iochrdy is not connected to the host, the data register should not be read before 370ns after the pointer was loaded to allow the data register fifo to fill. if the pointer is loaded using 8 bit writes , the low byte should be loaded first and the high byte last. eten when set, enables early transmit underrun detection. normal operation when clear. not empty when set, indicates that the write data fifo is not empty yet. the cpu can verify that the fifo is empty before loading a new pointer value. this is a read only bit. note: if auto incr. is not set, the pointer must be loaded with an even value.
41 i/o space - bank2 offset 8 through bh name data register type read/write symbol data 8 data 9 data a data b data data register used to read or write the data buffer byte/word presently addressed by the pointer register. this register is mapped into two uni -directional fifos that allow moving words to and from the LAN91C100 regardless of whether the pointer address is even, odd or dword aligned. data goes through the write fifo into memory, and is pre-fetched from memory into the read fifo. if byte accesses are used, the appropriate (next) byte can be accessed through the data low or data high registers. the order to and from the fifo is preserved. byte, word and dword accesses can be mixed on the fly in any order. this register is mapped into two consecutive word locations to facilitate double word move operations regardless of the actual bus width (16 or 32 bits). the data register is accessible at any address in the 8 through ah range, while the number of bytes being transferred are determined by a1 and nbe0-nbe3. the fifos are 12 bytes each.
42 i/o space - bank2 offset c name interrupt status register type read only symbol ist ercv int eph int rx_ovrn int alloc int tx empty int tx int rcv int x 0 0 0 0 1 0 0 offset c name interrupt acknowledge register type write only symbol ack ercv int rx_ovrn int tx empty int tx int offset d name interrupt mask register type read/write symbol msk ercv int eph int rx_ovrn int alloc int tx empty int tx int rcv int x 0 0 0 0 0 0 0 this register can be read and written as a word or as two individual bytes. the interrupt mask register bits enable the appropriate bits when high and disable them when low. an enabled bit being set will cause a hardware interrupt. ercv int early receive interrupt. set whenever a receive packet is being received, and the number of bytes received into memory exceeds the value programmed as ercv threshold (bank 3 , offset ch). ercv int stays set until acknowledged by writing the interrupt acknowledge register with the ercv int bit set. eph int set when the ethernet protocol handler section indicates one out of various possible special conditions. this bit merges exception type of interrupt sources, whose service time is not critical to the execution speed
43 of the low level drivers. the exact nature of the interrupt can be obtained from the eph status register (ephsr), and enabling of these sources can be done via the control register.
44 the possible sources are: link - link test transition ctr_rol - statistics counter roll over txena cleared - a fatal transmit error occurred forcing txena to be cleared. tx_suc will be low and the specific reason will be reflected by the bits: txunrn - transmit underrun sqet - sqe error lost carr - lost carrier latcol - late collision 16col - 16 collisions rx_ovrn int set when the receiver overruns due to a failed memory allocation. the rx_ovrn bit of the ephsr will also be set, but if a new packet is received it will be cleared. the rx_ovrn int bit, however, latches the overrun condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with the rx_ovrn int bit set. alloc int set when an mmu request for tx pages allocation is completed. this bit is the complement of the failed bit in the allocation result register. the alloc int enable bit should only be set following an allocation command, and cleared upon servicing the interrupt. tx empty int set if the tx fifo goes empty, can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission. this bit latches the empty condition, and the bit will stay set until it is specifically cleared by writing the acknowledge register with the tx empty int bit set. if a real time reading of the fifo empty is desired, the bit should be first cleared and then read. the tx empty int enable should only be set after the following steps: a) a packet is enqueued for transmission b) the previous empty condition is cleared (acknowledged) tx int set when at least one packet transmission was completed. the first packet number to be serviced can be read from the fifo ports register. the tx int bit is always the logic complement of the tempty bit in the fifo ports register. after servicing a packet number, its tx int interrupt is removed by writing the interrupt acknowledge register with the tx int bit set. rcv int set when a receive interrupt is generated. the first packet number to be serviced can be read from the fifo ports register. the rcv int bit is always the logic complement of the rempty bit in the fifo ports register. note: if the driver uses auto release mode it should enable tx empty int as well as tx int. tx empty int will be set when the complete sequence of packets is transmitted. tx int will be set if the sequence stops due to a fatal error on any of the packets in the sequence. note: for edge triggered systems, the interrupt service routine should clear the interrupt mask register, and only enable the appropriate interrupts after the interrupt source is serviced (acknowledged).
45
46 5 4 3 2 1 0 5 4 3 2 1 0 i n t e r r u p t s t a t u s r e g i s t e r i n t e r r u p t m a s k r e g i s t e r o e o e r d i s t 1 6 d a t a b u s d 0 - 7 d 8 - 1 5 e d g e d e t e c t o r o n l i n k e r r l e m a s k c t r - r o l c r m a s k t e m a s k t x e n a t x _ s v c e p h s r i n t e r r u p t s m e r g e d i n t o e p h i n t d 2 d 4 d s q q t x f i f o e m p t y w r a c k d s q q r x _ o v r n ( e p h s r ) a l l o c a t i o n f a i l e d t x c o m p l e t i o n f i f o n o t e m p t y r c v f i f o n o t e m p t y r c v i n t t x i n t t x e m p t y i n t a l l o c i n t r x _ o v r n i n t e p h i n t i n t m a i n i n t e r r u p t s e r c v i n t 6 6
47 figure 5 ? interrupt structure
48 i/o space - bank 3 offset 0 through 7 name multicast table type read/write symbol mt low byte multicast table 0 0 0 0 0 0 0 0 0 high byte multicast table 1 0 0 0 0 0 0 0 0 low byte multicast table 2 0 0 0 0 0 0 0 0 high byte multicast table 3 0 0 0 0 0 0 0 0 low byte multicast table 4 0 0 0 0 0 0 0 0 high byte multicast table 5 0 0 0 0 0 0 0 0 low byte multicast table 6 0 0 0 0 0 0 0 0 high byte multicast table 7 0 0 0 0 0 0 0 0
49 the 64 bit multicast table is used for group address filtering. the hash value is defined as the six most significant bits of the crc of the destination addresses. the three msb's determine the register to be used (mt0-7), while the other three determine the bit within the register. if the appropriate bit in the table is set, the packet is received. if the almul bit in the rcr register is set , all multicast addresses are received regardless of the multicast table values. hashing is only a partial group addressing filtering scheme, but being the hash value available as part of the receive status word, the receive routine can reduce the search time significantly. with the proper memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question.
50 i/o space - bank3 offset 8 name management interface type read/write symbol mgmt high byte 0 0 1 1 0 0 1 1 low byte mdoe mclk mdi mdo 0 0 1 1 0 0 mdi pin 0 mdoe mii management output enable. when high pin mdo is driven, when low pin mdo is tri-stated. mclk mii management clock. the value of this bit drives the mdclk pin. mdi mii management input. the value of the mdi pin is readable using this bit. mdo mii management output. the value of this bit drives the mdo pin. the purpose of this interface, along with the corresponding pins, is to implement mii phy management in software.
51 i/o space - bank3 offset a name revision register type read only symbol rev high byte 0 0 1 1 0 0 1 1 low byte chip rev 0 1 1 1 0 0 0 0 chip chip id. can be used by software drivers to identify the device used. rev revision id. incremented for each revision of a given device. chip id value device 3 lan91c90/lan91c92 7 LAN91C100 offset c name early rcv register type read/write symbol ercv high byte 0 0 1 1 0 0 1 1 low byte rcv discrd ercv threshold 0 0 0 1 1 1 1 1 rcv discrd set to discard a packet being received. ercv threshold threshold for ercv interrupt. specified in 64 byte multiples. whenever the number of bytes written in memory for the presently received packet exceeds the ercv threshold, ercv int bit of the interrupt status register is set.
52 i/o space - bank 7 offset 0 through 7 name external registers type symbol ncsout is driven low by the LAN91C100 when a valid access to the external register range occurs. high byte external r/w register low byte external r/w register cycle ncsout LAN91C100 data bus aen=0 a3=0 a4-15 matches i/o base bank select = 7 driven low. transparently latched on nads rising edge. ignored on writes. tri-stated on reads. bank select = 4,5,6 high ignore cycle. otherwise high normal LAN91C100 cycle.
53 typical flow of events for transmit s/w driver mac side 1 issue allocate memory for tx - n bytes - the mmu attempts to allocate n bytes of ram. 2 wait for successful completion code - poll until the alloc int bit is set or enable its mask bit and wait for the interrupt. the tx packet number is now at the allocation result register. 3 load transmit data - copy the tx packet number into the packet number register. write the pointer register, then use a block move operation from the upper layer transmit queue into the data register. 4 issue "enqueue packet number to tx fifo" - this command writes the number present in the packet number register into the tx fifo. the transmission is now enqueued. no further cpu intervention is needed until a transmit interrupt is generated. 5 the enqueued packet will be transferred to the mac block as a function of txena (n tcr) bit and of the deferral process state. 6 upon transmit completion the first word in memory is written with the status word. the packet number is moved from the tx fifo into the tx completion fifo. interrupt is generated by the tx completion fifo being not empty. 7 service interrupt - read interrupt status register. if it is a transmit interrupt, read the tx done packet number from the fifo ports register. write the packet number into the packet number register. the corresponding status word is now readable from memory. if status word shows successful transmission, issue release packet number command to free up the memory used by this packet. remove packet number from completion fifo by writing tx int acknowledge register.
54 typical flow of events for receiv e s/w driver mac side 1 enable reception - by setting the rxen bit. 2 a packet is received with matching address. memory is requested from mmu. a packet number is assigned to it. additional memory is requested if more pages are needed. 3 the internal dma logic generates sequential addresses and writes the receive words into memory. the mmu does the sequential to physical address translation. if overrun, packet is dropped and memory is released. 4 when the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. byte count is placed at the second word. if the crc checks correctly the packet number is written into the rx fifo. the rx fifo being not empty causes rcv int (interrupt) to be set. if crc is incorrect the packet memory is released and no interrupt will occur. 5 service interrupt - read the interrupt status register and determine if rcv int is set. the next receive packet is at receive area. (its packet number can be read from the fifo ports register). the software driver can process the packet by accessing the rx area, and can move it out to system memory if desired. when processing is complete the cpu issues the remove and release from top of rx command to have the mmu free up the used memory and packet number.
55 isr save bank select & address ptr registers mask smc91c100 interrupts read interrupt register call tx intr or txempty intr tx intr? get next tx rx intr? yes no no yes call rxintr alloc intr? no yes write allocated pkt # into packet number reg. write ad ptr reg. & copy data & source address enqueue packet packet available for transmission? yes no call allocate eph intr? no yes call eph intr set "ready for packet" flag return buffers to upper layer disable allocation interrupt mask restore address pointer & bank select registers unmask smc91c100 interrupts exit isr
56 figure 6 ? interrupt service routine
57 figure 7 ? rx intr rx intr write ad. ptr. reg. & read word 0 from ram destination multicast? read words 2, 3, 4 from ram for address filtering address filtering pass? status word ok? do receive lookahead get copy specs from upper layer okay to copy? copy data per upper layer specs issue "remove and release" command return to isr yes no yes no no yes no yes
58 write into packet number register tx status ok? tx intr save pkt number register read txdone pkt # from fifo ports reg. immediately issue "release" command acknowledge txintr read tx int again return to isr no yes read status word from ram update statistics re-enable txena update variables tx int = 0? restore packet number yes no write address pointer register
59 figure 8 ? tx intr
60 txempty intr write acknowledge reg. with txempty bit set read txempty & tx intr acknowledge txintr re-enable txena return to isr issue "release" command restore packet number txempty = 0 & txint = 0 (waiting for completion) txempty = x & txint = 1 (transmission failed) txempty = 1 & txint = 0 (everything went through successfully) read pkt. # register & save write address pointer register read status word from ram update statistics update variables
61 figure 9 ? txempty intr (assumes auto release selected)
62 allocate issue "allocate memory" command to mmu read interrupt status register enqueue packet set "ready for packet" flag return copy remaining tx data packet into ram return buffers to upper layer write allocated packet into packet # register write address pointer register copy part of tx data packet into ram write source address into proper location store data buffer pointer clear "ready for packet" flag enable allocation interrupt allocation passed? yes no driver send choose bank select register 2 call allocate exit driver send read allocation result register
63 figure 10 ? driver send and allocate routines
64 memory partitioning unlike other controllers, the LAN91C100 does not require a fixed memory partitioning between transmit and receive resources. the mmu allocates and de-allocates memory upon different events. an additional mechanism allows the cpu to prevent the receive process from starving the transmit memory allocation. memory is always requested by the side that needs to write into it, that is: the cpu for transmit or the mac for receive. the cpu can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive process is going to demand. furthermore, the receive process requests will be dependent on network traffic, in particular on the arrival of broadcast and multicast packets that might not be for the node, and that are not subject to upper layer software flow control. in order to prevent unwanted traffic from using too much memory, the cpu can program a "memory reserved for transmit" parameter. if the free memory falls below the "memory reserved for transmit" value, mmu requests from the mac block will fail and the packets will overrun and be ignored. whenever enough memory is released, packets can be received again. if the reserved value is too large, the node might lose data which is an abnormal condition. if the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. note that with the memory management built into the LAN91C100, the cpu can dynamically program this parameter. for instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory). whenever the driver needs to burst transmissions it can reduce the receive memory allocation. the driver program the parameter as a function of the following variables: 1) free memory (read only register) 2) memory size (read only register) the reserved memory value can be changed on the fly. if the memory reserved for tx value is increased above the free memory, receive packets in progress are still received, but no new packets are accepted until the free memory increases above the memory reserved value. interrupt generation the interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller. for that purpose there is no register reading necessary before the next element in the queue (namely transmit or receive packet) can be handled by the controller. the transmit and receive results are placed in memory. the receive interrupt will be generated when the receive queue (fifo of packets) is not empty and receive interrupts are enabled. this allows the interrupt service routine to process many receive packets without exiting, or one at a time if the isr just returns after processing and removing one. there are two types of transmit interrupt strategies: 1) one interrupt per packet. 2) one interrupt per sequence of packets. the strategy is determined by how the transmit interrupt bits and the auto release bit are used. tx int bit - set whenever the tx completion fifo is not empty. tx empty int bit - set whenever the tx fifo is empty.
65 auto release - when set, successful transmit packets are not written into completion fifo, and their memory is released automatically. 1) one interrupt per packet: enable tx int, set auto release=0. the software driver can find the completion result in memory and process the interrupt one packet at a time. depending on the completion code the driver will take different actions. note that the transmit process is working in parallel and other transmissions might be taking place. the LAN91C100 is virtually queuing the packet numbers and their status words. in this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the tx done packet number at the fifo ports register. this eliminates the need for the driver to keep a list of packet numbers being transmitted. the numbers are queued by the LAN91C100 and provided back to the cpu as their transmission completes. 2) one interrupt per sequence of packets: enable tx empty int and tx int, set auto release=1. tx empty int is generated only after transmitting the last packet in the fifo. tx int will be set on a fatal transmit error allowing the cpu to know that the transmit process has stopped and therefore the fifo will not be emptied. this mode has the advantage of a smaller cpu overhead, and faster memory de-allocation. note that when auto release=1 the cpu is not provided with the packet numbers that completed successfully. note: the pointer register is shared by any process accessing the LAN91C100 memory. in order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt. typically there would be three processes using the pointer: 1) transmit loading (sometimes interrupt driven) 2) receive unloading (interrupt driven) 3) transmit status reading (interrupt driven). 1) and 3) also share the usage of the packet number register. therefore saving and restoring the pnr is also required from interrupt service routines.
66 t x f i f o t x c o m p l e t i o n f i f o r x f i f o c s m a / c d l o g i c a l a d d r e s s p a c k e t # m m u p h y s i c a l a d d r e s s r a m cpu address csma address rx packet number rx fifo packet number packet number register pack # out m.s. bit only 'empty' 'not empty' tx done packet number 'not empty' interrupt status register rcv int tx empty int tx int alloc int two options
67 figure 11 ? interrupt generation for transmit, receive, mmu
68 board setup information the following parameters are obtained from the eeprom as board setup information: ethernet individual address i/o base address 10base-t or aui interface mii or endec interface interrupt line selection all the above mentioned values are read from the eeprom upon hardware reset. except for the individual address, the value of the ios switches determines the offset within the eeprom for these parameters, in such a way that many identical boards can be plugged into the same system by just changing the ios jumpers. in order to support a software utility based installation, even if the eeprom was never programmed, the eeprom can be written using the LAN91C100. one of the ios combination is associated with a fixed default value for the key parameters (i/o base, interrupt) that can always be used regardless of the eeprom based value being programmed. this value will be used if all ios pins are left open or pulled high. the eeprom is arranged as a 64 x 16 array. the specific target device is the 9346 1024-bit serial eeprom. all eeprom accesses are done in words. all eeprom addresses in the spec are specified as word addresses. individual address 20-22 hex if ios2-0 = 7 , only the individual address is read from the eeprom. currently assigned values are assumed for the other registers. these values are default if the eeprom read operation follows hardware reset. the eeprom select bit is used to determine the type of eeprom operation : a) normal or b) general purpose register. a) normal eeprom operation - eeprom select bit = 0 on eeprom read operations (after reset or after setting reload high) the configuration register and base register are updated with the eeprom values at locations defined by the ios2-0 pins. the individual address registers are updated with the values stored in the individual address area of the eeprom. register eeprom word address configuration register base register ios value * 4 (ios value * 4) + 1
69 on eeprom write operations (after setting the store bit) the values of the configuration register and base register are written in the eeprom locations defined by the ios2-0 pins. the three least significant bits of the control register (eeprom select, reload and store) are used to control the eeprom. their values are not stored nor loaded from the eeprom. b) general purpose register - eeprom select bit = 1 on eeprom read operations (after setting reload high) the eeprom word address defined by the pointer register 6 least significant bits is read into the general purpose register. on eeprom write operations (after setting the store bit) the value of the general purpose register is written at the eeprom word address defined by the pointer register 6 least significant bits. reload and store are set by the user to initiate read and write operations respectively. polling the value until read low is used to determine completion. when an eeprom access is in progress the store and reload bits of ctr will readback as both bits high. no other bits of feast can be read or written until the eeprom operation completes and both bits are clear. this mechanism is also valid for reset initiated reloads. note: if no eeprom is connected to the lan91c900, for example for some embedded applications, the eneep pin should be grounded and no accesses to the eeprom will be attempted. configuration, base, and individual address assume their default values upon hardware reset and the cpu is responsible for programming them for their final value.
70 configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. ia0-1 ia2-3 ia4-5 ios2-0 word address 000 0h 1h 4h 5h 8h 9h ch dh 10h 11h 14h 15h 18h 19h 20h 21h 22h 001 010 011 100 101 110 xxx 16 bits
71 figure 12 ? 64 x 16 serial eeprom map
72 application considerations the LAN91C100 is envisioned to fit a few different bus types. this section describes the basic guidelines, system level implications and sample configurations for the most relevant bus types. all applications are based on buffered architectures with a private sram bus. fast ethernet slave adapter slave non-intelligent board implementing 100 mbps and 10 mbps speeds. adapter requires: a) LAN91C100 fast ethernet controller b) four srams (32k x 8 - 25ns) c) serial eeprom (93c46) d) 10 mbps endec and transceiver chip e) 100 mbps mii compliant phy f) some bus specific glue logic target systems: a) vl local bus 32 bit systemsa) vl local bus 32 bit systems) vl local bus 32 bit systems) vl local bus 32 bit systems b) high-e nd isa machines c) eisa 32 bit slave vl local bus 32 bit systems on vl local bus and other 32 bit embedded systems, the LAN91C100 is accessed as a 32 bit peripheral in terms of the bus interface. all registers except the data register will be accessed using byte or word instructions. accesses to the data register could use byte, word, or dword instructions. table 3 - vl local bus signal connections vl bus signal LAN91C100 signal notes a2-a15 a2-a15 address bus used for i/o space and register decoding, latched by nads rising edge, and transparent on nads low time m/ nio aen qualifies valid i/o decoding - enabled access when low. this signal is latched by nads rising edge and transparent on nads low time w/ nr w/ nr direction of access. sampled by the LAN91C100 on first rising clock that has ncycle active. high on writes, low on reads. nrdyrtn nrdyrtn ready return. direct connection to vl bus. nlrdy nsrdy and some logic nsrdy has the appropriate functionality and timing to create the vl nlrdy except that nlrdy behaves like an open drain output most of the time.
73 table 3 - vl local bus signal connections vl bus signal LAN91C100 signal notes lclk lclk local bus clock. rising edges used for synchronous bus interface transactions. nreset reset connected via inverter to the LAN91C100. nbe0 nbe1 nbe2 nbe3 nbe0 nbe1 nbe2 nbe3 byte enables. latched transparently by nads rising edge. nads nads, ncycle address strobe is connected directly to the vl bus. ncycle is created typically by using nads delayed by one lclk. irqn intr0-intr3 typically uses the interrupt lines on the isa edge connector of vl bus. d0-d31 d0-d31 32 bit data bus. the bus byte(s) used to access the device are a function of nbe0-nbe3: be0 be1 nbe 2 be3 0 0 1 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 0 double word access low word access high word access byte 0 access byte 1 access byte 2 access byte 3 access n not used = tri-state on reads, ignored on writes. note that nbe2 and nbe3 override the value of a1, which is tied low in this application. nldev nldev nldev is a totem pole output. nldev is active on valid decodes of a15-a4 and aen=0. unused pins vcc nrd, nwr gnd a1, nvlbus open ndatacs
74 high-end isa machines on isa machines, the LAN91C100 is accessed as a 16 bit peripheral. no support for xt (8 bit peripheral) is provided. the signal connections are listed in the following table: table 4 - high-end isa machines signal connections isa bus signal LAN91C100 signal notes a1-a15 a1-a15 address bus used for i/o space and register decoding aen aen qualifies valid i/o decoding - enabled access when low niord nrd i/o read strobe - asynchronous read accesses. address is valid before leading edge niowr nwr i/o write strobe - asynchronous write access. address is valid before leading edge. data is latched on trailing edge iochrdy ardy this signal is negated on leading nrd, nwr if necessary. it is then asserted on clk rising edge after the access condition is satisfied. reset reset a0 nbe0 nsbhe nbe1 irqn intr0-intr3 d0-d15 d0-d15 16 bit data bus. the bus byte(s) used to access the device are a function of nbe0 and nbe1: nbe0 nbe1 d0-d7 d8-d15 0 0 1 0 1 0 lower lower not used upper not used upper not used = tri-state on reads, ignored on writes. niocs16 nldev buffered nldev is a totem pole output. must be buffered using an open collector driver. nldev is active on valid decodes of a15-a4 and aen=0.
75 table 4 - high-end isa machines signal connections isa bus signal LAN91C100 signal notes unused pins vcc nbe2, nbe3, ncycle, w/nr nrdyrtn no upper word access. gnd lclk, nads open d16-d31, ndatacs, nvlbus
76 eisa 32 bit slaveeisa 32 bit slaveeisa 32 bit slaveeisa 32 bit slaveeisa 32 bit slaveeisa 32 bit slaveeisa 32 bit slaveeisa 32 bit slaveeisa 32 bit slave on eisa, the LAN91C100 is accessed as a 32 bit i/o slave, along with a slave dma type "c" data path option. as an i/o slave, the LAN91C100 uses asynchronous accesses. in creating nrd and nwr inputs, the timing information is externally derived from ncmd edges. given that the access will be at least 1.5 to 2 clocks (more than 180ns at least) there is no need to negate exrdy, simplifying the eisa interface implementation. as a dma slave, the LAN91C100 accepts burst transfers, and is able to sustain the peak rate of one doubleword every bclk. doubleword alignment is assumed for dma transfers. up to 3 extra bytes in the beginning and at the end of the transfer should be moved by the cpu using i/o accesses to the data register. the LAN91C100 will sample exrdy and postpone dma cycles if the memory cycle solicits wait states. table 5 - eisa 32 bit slave signal connections eisa bus signal LAN91C100 signal notes la2-15 a2-a15 address bus used for i/o space and register decoding, latched by nads (nstart) trailing edge. m/nio aen aen qualifies valid i/o decoding - enabled access when low. these signals are externally ored. internally the aen pin is latched by nads rising edge and transparent while nads is low. latched w-r combined with ncmd nrd i/o read strobe - asynchronous read accesses. address is valid before its leading edge. must not be active during dma bursts if dma is supported. latched w-r combined with ncmd nwr i/o write strobe - asynchronous write access. address is valid before leading edge. data latched on trailing edge. must not be active during dma bursts if dma is supported. nstart nads address strobe is connected to eisa nstart. resdrv reset nbe0, nbe1, nbe2, nbe3 nbe0, nbe1, nbe2, nbe3 byte enables. latched on nads rising edge. irqn intr0-intr3 interrupts used as active high edge triggered.
77 table 5 - eisa 32 bit slave signal connections eisa bus signal LAN91C100 signal notes d0-d31 d0-d31 32 bit data bus. the bus byte(s) used to access the device are a function of nbe0-nbe3: nbe 0 nbe 1 nbe 2 nbe 3 0 0 1 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 0 double word access low word access high word access byte 0 access byte 1 access byte 2 access byte 3 access not used = tri-state on reads, ignored on writes. note that nbe2 and nbe3 override the value of a1, which is tied low in this application. other combinations of nbe are not supported by the LAN91C100. s/w drivers are not anticipated to generate them. nex32 nnows (optional additional logic) nldev nldev is a totem pole output. nldev is active on valid decodes of the LAN91C100's pins a15-a4 and aen=0. nnows is similar to nldev except that it should go inactive on nstart rising. nnows can be used to request compressed cycles (1.5 bclk long, nrd/nwr will be 1/2 bclk wide). the following signals support slave dma type "c" burst cycles bclk lclk eisa bus clock. data transfer clock for dma bursts. ndak ndatacs dma acknowledge. active during slave dma cycles. used by the LAN91C100 as ndatacs direct access to data path. niorc w/nr indicates the direction and timing of the dma cycles. high during LAN91C100 writes; low during LAN91C100 reads. niowc ncycle indicates slave dma writes. nexrdy nrdyrtn eisa bus signal indicating whether a slave dma cycle will take place on the next bclk rising edge, or should be postponed. nrdyrtn is used as an input in the slave
78 dma mode to bring in exrdy.
79 table 5 - eisa 32 bit slave signal connections eisa bus signal LAN91C100 signal notes unused pins vcc nvlbus gnd a1 open
69 operational description maximum guaranteed ratings* operating temperature range ................................ ................................ ........................ 0oc to +70oc storage temperature range ................................ ................................ ...................... -55oc to +150oc lead temperature range (soldering, 10 seconds) ................................ ................................ ... +325oc positive voltage on any pin, with respect to ground ................................ ............................ v cc + 0.3v negative voltage on any pin, with respect to ground ................................ ................................ ... -0.3v maximum v cc ................................ ................................ ................................ ............................... +7v *stresses above those listed above could cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. note: when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. dc electrical characteristics (t a = 0oc - 70oc, v cc = +5.0 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger i clk input buffer low input level high input level v il ck v ihck 3.0 0.4 v v
70 parameter symbol min typ max units comments input leakage (all i and is buffers except pins with pullups/pulldowns) low input leakage high input leakage i il i ih -10 -10 +10 +10 a a v in = 0 v in = v cc ip type buffers input current i il -150 -75 a v in = 0 id type buffers input current i ih +75 +150 a v in = v cc o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc i/o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc o12 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 12 ma i oh = -6 ma v in = 0 to v cc o16 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 16 ma i oh = -8 ma v in = 0 to v cc
71 parameter symbol min typ max units comments od16 type buffer low output level output leakage v ol i ol -10 0.5 +10 v a i ol = 16 ma v in = 0 to v cc o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 24 ma i oh = -12 ma v in = 0 to v cc i/o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 24 ma i oh = -12 ma v in = 0 to v cc supply current active supply current standby i cc i csby 60 8 95 ma ma all outputs open. capacitance t a = 25oc; fc = 1mhz; v cc = 5v limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf all pins except pin under test tied to ac ground input capacitance c in 10 pf output capacitance c out 20 pf capacitive load on outputs nardy, d0-d31 (non vlbus) 240 pf d0-d31 in vlbus 45 pf all other outputs 45 pf
72 timing diagrams parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup to nrd, nwr active 25 ns t2 a1-a15, aen, nbe0-nbe3 hold after nrd, nwr inactive (assuming nads tied low) 20 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns t5 t2 t3 t4 t1 t5a a1-15, aen,nbe0-nbe3 valid d0-d31 valid address nads read data nrd,nwr write data figure 13 - asynchronous cycle - nads = 0
73 parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup to nrd, nwr active 25 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t8 t9 t5 t3 t4 t1 t5a a1-a15, aen,nbe0-nbe3 valid d0-d31 valid address nads read data nrd, nwr write data figure 14 - asynchronous cycle - using nads
74 parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup to nrd, nwr active 25 ns t2 a1-a15, aen, nbe0-nbe3 hold after nrd, nwr inactive (assuming nads tied low) 20 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns t5 t2 t3 t4 t1 t5a d0-d31 valid ndatacs nads read data nrd, nwr write data figure 15 - asynchronous cycle - nads = 0 (ndatacs used to select data register; must be 32 bit access)
75 parameter min typ max units t12 ndatacs setup to either ncycle or w/nr falling 60 ns t13 ndatacs hold after either ncycle or w/nr rising 30 ns t14 nrdyrtn setup to lclk falling 15 ns t15 nrdyrtn hold after lclk falling 2 ns t17 ncycle high and w/nr high overlap 50 ns t18 data setup to lclk rising (write) 13 ns t20 data hold from lclk rising (write) 5 ns t12 t18 t20 t14 t15 t13 t17 t17 a b c lclk ndatacs w/nr ncycle write data nrdyrtn figure 16 - burst write cycles - nvlbus = 1
76 parameter min typ max units t12 ndatacs setup to either ncycle or w/nr falling 60 ns t13 ndatacs hold after either ncycle or w/nr rising 30 ns t14 nrdyrtn setup to lclk falling 15 ns t15 nrdyrtn hold after lclk falling 2 ns t17 ncycle high and w/nr high overlap 50 ns t19 data delay from lclk rising (read) 5 38 ns t12 t14 t15 t13 t17 t19 t17 c a b lclk ndatacs w/nr read data nrdyrtn ncycle figure 17 - burst read cycles - nvlbus = 1
77 parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t25 a4-a15, aen to nldev delay 20 ns t8 t9 t25 a1-15,aen,nbe0-nbe3 nads address nldev figure 18 - address latching for all modes
78 parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t10 ncycle setup to lclk rising 7 ns t18 t20 t10 t11 t17a t9 t8 t16 t21 t21 d0-d31 valid a1-15,aen,nbe0-nbe3 lclk w/nr address nads ncycle write data nsrdy ndatacs figure 19 - synchronous write cycle - nvlbus = 0
79 t11 ncycle hold after lclk rising (non-burst mode) 3 ns t16 w/nr setup to ncycle active 30 ns t17a w/nr hold after lclk rising with nlrdy active 5 ns t18 data setup to lclk rising (write) 13 ns t20 data hold from lclk rising (write) 5 ns t21 nlrdy delay from lclk rising 10 ns
80 t20 t23 t24 t10 t11 t9 t8 t16 t21 t21 d0-d31 valid a1-15,aen,nbe0-nbe3 lclk w/nr address nads ncycle read data nsrdy rdyrtn ndatacs figure 20 - synchronous read cycle - nvlbus = 0
81 parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t10 ncycle setup to lclk rising 7 ns t11 ncycle hold after lclk rising (non-burst mode) 3 ns t16 w/nr setup to ncycle active 30 ns t20 data hold from lclk rising (write) 5 ns t21 nlrdy delay from lclk rising 10 ns t23 nrdyrtn setup to lclk rising 7 ns t24 nrdyrtn hold after lclk rising 3 ns
82 parameter min typ max units t34 ra2-ra16nn setup to nrwe-0-nrwe3 falling 0 ns t35 ra2-ra16nn hold after nrwe-0-nrwe3, nroe rising 0 ns t36 write - rd0-rd31 setup to nrwe0-nrwe3 rising 12 ns t37 write - rd0-rd31 hold after nrwe0-nrwe3 rising 0 ns t38 read - ra2-ra16 valid to rd0-rd31 valid 25 ns t34 t35 t36 t37 t38 write cycle read cycle data out data in ra2-ra16 rnwe0-nrwe3 nroe rd0-rd31 figure 21 - sram interface
83 parameter min typ max units t30 txd, txen delay from txc rising 0 40 ns t31 nrxd setup to rxc rising 10 ns t32 rxd hold after rxc rising 30 ns notes: 1. crs input might be asynchronous to rxc. 2. rxc starts after crs goes active. rxc stops after crs goes inactive. 3. col is an asynchronous input. t31 t30 t30 t30 t32 txc txen txd rxd rxc crs figure 22 - endec interface - 10 mbps
84 parameter min typ max units t27 txd0-txd3, txen100 delay from tx25 rising 0 15 ns t28 rxd0-rxd3, rx_dv, rx_er setup to rx25 rising 10 ns t29 rxd0-rxd3, rx_dv, rx_er hold after rx25 rising 10 ns t28 t28 t28 t27 t27 t29 t29 tx25 txd0-3 txen100 rxd0-3 rx25 rx_dv rx_er figure 23 - mii interface
85 see detail 'a' 52 d d1 3 156 105 104 3 157 detail 'a' r1 r2 4 l l1 5 e e1 208 1 1 0.10 c h a1 a a2 53 e 2 w d1/4 e1/4 0 notes: coplanarity is 0.100mm maximum. tolerance on the position of the leads is 0.08mm maximum. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25mm. dimension for foot length l when measured at the centerline of the leads are given in the table. dimension for foot length l when measured at the gauge plane 0.25mm above the seating plane, is 0.6mm. details of pin 1 identifier are optional but must be located within the zone indicated. 6. controlling dimension: millimeter 1 2 3 4 5 min 0.05 3.17 30.35 27.90 30.35 27.90 0.09 0.35 nom 30.60 28.00 30.60 28.00 0.5 1.30 max 4.07 0.5 3.67 30.85 28.10 30.85 28.10 0.23 0.65 0 0.10 0.25 0.20 0.20 0.50 bsc 7 0.30 dim a a1 a2 d d1 e3 e1 h l l1 e 0 w r1 r2
86 figure 24 - 208 pin pqfp package outlines
87 1 2 3 4 5 nom 30.00 15.00 28.00 30.00 15.00 28.00 0.60 1.00 0.50 bsc dim a a1 a2 d d/2 d1 e e/2 e1 h l l1 e 0 w r1 r2 ccc ccc remark overall package height standoff body thickness x span 1/2 x span measure from centerline x body size y span 1/2 y span measure from centerline y body size lead frame thickness lead foot length from centerline lead length lead pitch lead foot angle lead width lead shoulder radius lead foot radius coplanarity (assemblers) coplanarity (test house) min 0.05 1.35 29.80 14.90 27.90 29.80 14.90 27.90 0.09 0.45 0 0.17 0.08 0.08 max 1.60 0.15 1.45 30.20 15.10 28.10 30.20 15.10 28.10 0.23 0.75 7 0.27 0.20 0.0762 0.08 notes: controlling unit: millimeter. tolerance on the position of the leads is 0.04mm maximum. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25mm. dimension for foot length l measured at the gauge plane 0.25mm above the seating plane, is 0.78-1.08mm. details of pin 1 identifier are optional but must be located within the zone indicated.
88 figure 25 ? 208 pin tqfp package outlines

1997 standard microsystems corp. circuit diagrams utilizing smsc products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. the information has been carefully checked and is believed to be entirely reliable. however, no responsibility is assumed for inaccuracies. furthermore, such information does not convey to the purchaser of the semiconduc tor devices described any licenses under the patent rights of smsc or others. smsc reserves the right to make changes at any time in order to improve design and supply the best product possible. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. LAN91C100 rev. 9/24/97

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